[RISCV] Don't overcost wide load in optimized segment load/store (#207146)
With the +optimized-nfX-segment-load-store tuning flag, we cost a
segmented store as a single wide load + some shuffle ops.
However for e.g. a `<vscale x 5 x i64>` Factor=5 segmented load, a wide
`<vscale x 5 x i64>` load gets costed as a full LMUL 8 load.
From what I can see on
https://camel-cdr.github.io/rvv-bench-results/spacemit_x100/index.html
and on my own measurements on the spacemit-x60, uarchs likely don't do a
full LMUL 8 load under the hood and instead dispatch the minimum number
of DLEN sized ops needed for the full segment.
This changes the wide load cost to be divideCeil(vector size, DLEN) ops
so we don't overcost it.
Whilst we're here, this also removes the LT.first legalization
multiplier. We're computing the cost in terms of the unlegalized type so
we shouldn't be scaling it by the legalization cost.
llvm-project
bd439d56 - [RISCV] Don't overcost wide load in optimized segment load/store (#207146)
