[MLIR][NVVM] Update nvvm.barrier.arrive Op (#202608)
This change updates the `nvvm.barrier.arrive` Op to lower using
intrinsics instead of inline PTX. It also adds a new `aligned` attribute
to the Op to lower to both aligned and unaligned forms.
PTX Spec Reference:
https://docs.nvidia.com/cuda/parallel-thread-execution/#parallel-synchronization-and-communication-instructions-bar
