llvm-project

c1ac2e0c - AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints

AMDGPU: Use RegClassByHwMode to manage operand VGPR operand constraints This removes special case processing in TargetInstrInfo::getRegClass to fixup register operands which depending on the subtarget support AGPRs, or require even aligned registers. This regresses assembler diagnostics, which currently work by hackily accepting invalid cases and then post-rejecting a validly parsed instruction. On the plus side this now emits a comment when disassembling unaligned registers for targets with the alignment requirement.