llvm-project

c22bc215 - [MIPS] Reland Scheduling model for MIPS i6400 and i6500 CPUs (#132704) (#137984)

[MIPS] Reland Scheduling model for MIPS i6400 and i6500 CPUs (#132704) (#137984) Relands #132704 with a fix in the testcase: Add llvm/test/tools/llvm-mca/Mips/lit.local.cfg Add scheduling model for the MIPS i6400 and i6500, an in-order MIPS64R6 processor. i6400 and i6500 share same instruction latencies. CPU has following pipelines - Two ALUs - Multiply and Divide unit (MDU) - Branch Unit (CTU) - Load/Store Unit (LSU) - Short Floating-point Unit and - Long Floating-point Unit Latency information is available at: https://mips.com/wp-content/uploads/2025/03/MIPS_I6500-F_Data_Sheet_Rev1.10_3-17-2025.pdf