llvm-project

c5470e0f - [RISC-V][MC] Fix tied operand register class mismatch in P-extension

[RISC-V][MC] Fix tied operand register class mismatch in P-extension I have a change to validate the operand classes emitted in the AsmParser and that caused llvm/test/MC/RISCV/rv32p-valid.s to fail due to the rd_wb register using a different register class from rd: `PWADDA_H operand 1 register X6 is not a member of register class GPRPair` This happens because tablegen's AsmMatcherEmitter emits code to literally copy over the tied registers and does not feed them through the equivalent of RISCVAsmParser::validateTargetOperandClass() which would allow adjusting these operand classes. Ideally we would handle this in tablegen (or at least add an error), but the tied operand handling logic is rather complex and I don't understand it yet. For now just update the rd register class to match rd_wb. Pull Request: https://github.com/llvm/llvm-project/pull/171738