llvm-project

c5aac536 - [TableGen][AsmMatcher] Support generated register coercion logic (#241022)

[TableGen][AsmMatcher] Support generated register coercion logic (#241022) When multiple `RegisterClass`es share assembly register names (for example as the RISC-V sub/super-register FP classes, vector register groups, or GPR/YGPR), this currently needs to be resolved inside `validateTargetOperandClass`. One downside of the current approach is that we end up mutating a RegisterOperand before we have determined whether it will actually end up being used by the instruction we end up selecting. Add a new `CoerceFromRegClass` field on `RegisterClass` so TableGen can generate the `MCRegister` conversion in `convertToMCInst` automatically. Once all operands pass `validateOperandClass`, the matched instruction's ConversionTable row knows the target RegisterClass and emits the appropriate `convertTo*` call in `convertToMCInst` (without ever calling validateTargetOperandClass), which avoids mutating partially parsed operands. Follow-up commits will use this feature to simplify the RISC-V AsmParser, and I also have changes for other targets. Assisted-by: AI tooling Pull-Request: https://github.com/llvm/llvm-project/pull/241022