llvm-project

cbf0f6f9 - [RISCV] Materialize rotated LUI values with LUI+RORI (#240099)

[RISCV] Materialize rotated LUI values with LUI+RORI (#240099) RISCVMatInt already uses RORI (or TH_SRRI) when a constant rotated left fits in 12 bits, materializing it as ADDI+RORI. Extend this to constants that rotate into a sign-extended 32-bit value with zero low 12 bits, which LUI can load directly, and materialize them as LUI+RORI. These are masks that wrap around bit 63 and the tagged or boxed constants of JIT compilers. For example 0xfffc000000000001 now takes ``` lui a0, 32767 rori a0, a0, 26 ``` instead of li+slli+addi. Found via riscvlint. Assisted-by: Claude Code (Claude Fable 5.1)