llvm-project

ceb0e18c - [MLIR][XeVM] Support all SPIR-V vector lengths in truncf and extf (#217768)

[MLIR][XeVM] Support all SPIR-V vector lengths in truncf and extf (#217768) The fp8 and fp4 conversions only lowered a 16 element vector. Lower every SPIR-V vector length, 2, 3, 4, 8 and 16, for both formats and for f16 and bf16 operands, following IGC's SPV_INTEL_fp_conversions implementation. Two fp4 values pack into a single byte, and SPIR-V uses a scalar where it has no one element vector, so the packed side of that conversion is a scalar. The verifier previously required both operands to be vectors or both scalars, which rejected it. It now checks that the packed side is exactly wide enough to hold the values it carries, which both permits that case and catches mismatched lengths that used to pass. Also fixes two latent bugs in the shuffle legalization that the new IR reaches: a null dereference when a shuffle reads a bitcast of a scalar, and a mask computed by a division that could drop a remainder, which built an invalid shuffle when the extracted slice did not cover whole source elements. Adds conversion tests for each length, and end to end round trip tests for both formats with f16 and bf16 operands.