llvm-project

d6feecab - [AMDGPU] Initialize FrameOffsetReg for amdgpu_cs_chain functions

[AMDGPU] Initialize FrameOffsetReg for amdgpu_cs_chain functions Functions with the amdgpu_cs_chain calling convention were not initializing FrameOffsetReg, leaving it as FP_REG. This caused machine code verification failures as SCRATCH_STORE_DWORD_SADDR instructions require the saddr operand to be in the SReg_32_XEXEC_HI register class. This LLVM defect was identified via the AMD Fuzzing project.