llvm-project

d72cec5b - [AArch64][llvm] Gate some `tlbip` insns with +tlbid or +d128

[AArch64][llvm] Gate some `tlbip` insns with +tlbid or +d128 Change the gating of `tlbip` instructions containing `*E1IS*`, `*E1OS*`, `*E2IS*` or `*E2OS*` to be used with `+tlbid` or `+d128`. This is because the 2025 Armv9.7-A MemSys specification says: ``` All TLBIP *E1IS*, TLBIP*E1OS*, TLBIP*E2IS* and TLBIP*E2OS* instructions that are currently dependent on FEAT_D128 are updated to be dependent on FEAT_D128 or FEAT_TLBID ```