llvm-project

d7b590b8 - [RISCV] Ensure false dominates in vmerge peephole (#181664)

[RISCV] Ensure false dominates in vmerge peephole (#181664) When folding vmerge into it's true operand, true will eventually use the false operand as its passthru, but we don't check that the instruction defining false dominates true. This can cause a use before def. Fix this by sinking true past false. We already do this for the mask, so this does it in the same call to ensureDominates. We don't seem to run into this with current codegen but upcoming changes to RISCVVLOptimizer expose it.