llvm-project

dc2ed004 - [RISCV] Handle non uimm5 VL constants in isVLKnownLE (#156639)

[RISCV] Handle non uimm5 VL constants in isVLKnownLE (#156639) If a VL operand is > 31 then it will be materialized into an ADDI $x0, imm. We can reason about it by peeking at the virtual register definition which allows RISCVVectorPeephole and RISCVVLOptimizer to catch more cases. There's a separate issue with RISCVVLOptimizer where the materialized immediate may not always dominate the instruction we want to reduce the VL of, but this is left to another patch.