[RISCV] Fold (add (srl x, n), (srl x, n)) into (srl x, n-1)
This patch adds a new fold that will turn
(add (srl x, n), (srl x, n))
into
(srl x, n-1)
when bit n-1 is known to be zero in x.
This could perhaps be moved to generic DAGCombiner in the
future, but this patch adds it as a RISCV specific combine.
For RISCV it typically trigger for DAG nodes like this that
may be created by the legalizer:
t1: i32 = srl RISCVISD::READ_VLENB:i32, Constant:i32<2>
t2: i32 = add t1, t1
Got the idea when working on a solution for #141034, as it
may avoid some regressions otherwise caused by the fix being
prepared for that issue.
llvm-project
ef9547df - [RISCV] Fold (add (srl x, n), (srl x, n)) into (srl x, n-1)
