llvm-project
f0c9acc3 - [SPIRV][HLSL] Add FixedVector GEP legalization (#171682)

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5 days ago
[SPIRV][HLSL] Add FixedVector GEP legalization (#171682) fixes #170241 PR #169090 updated vector swizzle elements individually for HLSL This is because rawbuffer writes via rawBufferStore can cause datarace in concurrent writing the way vectors are written all at once. This means we needed individual writes per element. So that means we need to be able to GEP into an element of a vector. The SPIRV backend did not support this pattern. SPIRV assumes Composite types (ie Vectors, Structs, and Arrays) only for Ptr legalization in it's store transformations via transformStore. Fixing things at the point of ptr legalziation for the store would be too late because we would have lost critical ptr type information still available in LLVM IR. Instead what we needed to do is teach the walkLogicalAccessChain used by buildLogicalAccessChainFromGEP to converts a byte-offset GEP on an i8-pointer into a logical SPIR-V composite access chain. In short: The fundamental issue is that walkLogicalAccessChain currently refuses to handle vector-based logical GEPs, but Clang’s new HLSL path produces exactly that pattern: - you have a logical i8* GEP that represents indexing into the elements of a <4 x i32>. We need to teach walkLogicalAccessChain to treat a FixedVectorType similarly to an array of its element type. So in walkLogicalAccessChain replace the “give up on vector” part with logic that: - Interprets the byte Offset as indexing into the vector elements. - Uses the vector’s element type and number of elements.
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