llvm-project

f3f717bb - [RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191)

[RISCV] Add computeKnownBitsForTargetNode for RISCVISD::SRAW. (#156191) This node reads the lower 32 bits, shifts it right arithmetically then sign extends to i64. If we know some of the lower 32 bits we can propagate that information. For the test case I had to find something that didn't get optimized before type legalizaton and didn't get type legalized to a sign extended value. The bswap gets type legalized to (lshr (bswap), 32).