llvm-project

f80205be - [mlir][SPIRV] Add sub-element-byte lowering support for atomic_rmw ori/andi ops (#179831)

[mlir][SPIRV] Add sub-element-byte lowering support for atomic_rmw ori/andi ops (#179831) When the memref element type (e.g., i8) is narrower than the SPIR-V storage type (e.g., i32 on Vulkan), ori and andi can be lowered with a single wide atomic instruction because OR-with-0 and AND-with-1 are identity operations. The revision follows `IntStoreOpPattern` to compute offsets/sizes via `adjustAccessChainForBitwidth` method and `getOffsetForBitwidth` method. Additionally, it handles the returned value (which is the old value by definition), which is different from `IntStoreOpPattern`. E.g., the check of `spirv::Capability::Kernel` is the same. https://github.com/llvm/llvm-project/blob/07ebb18e07fb9e009b1f738d6214a49c7bbe8fee/mlir/lib/Conversion/MemRefToSPIRV/MemRefToSPIRV.cpp#L847-L867 There are refactoring opportunities and it is not performed within the revision because the current implementation is already complicated. The refactoring can be happenned in a follow-up with its own patch, so reviewing this revision is easier. Signed-off-by: hanhanW <hanhan0912@gmail.com> --------- Signed-off-by: hanhanW <hanhan0912@gmail.com>