llvm-project

f92bfca9 - [AArch64] All bits of an exact right shift are demanded (#97448)

[AArch64] All bits of an exact right shift are demanded (#97448) When building a vector which contains zero elements, the AArch64 ISel replaces those elements with `undef`, if they are right shifted out. However, these elements need to stay zero if the right shift is exact, or otherwise we will be introducing undefined behavior. Should allow https://github.com/llvm/llvm-project/pull/92528 to be recommitted.