llvm-project

fcefee01 - AMDGPU: llvm.amdgcn.ds.add/sub.gs.reg.rtn are sources of divergence (#186883)

AMDGPU: llvm.amdgcn.ds.add/sub.gs.reg.rtn are sources of divergence (#186883) Per the ISA documentation, these are atomic operations on dedicated GS streamout registers. As GDS instructions, the first active lane (based on EXEC) is used and others are ignored.