onnxruntime

02789a58 - webgpu: two optimizations for the subgroup Gemm/MatMul kernels: (#29271)

webgpu: two optimizations for the subgroup Gemm/MatMul kernels: (#29271) 1. Double-buffer the B tile in workgroup memory when type is float16. 2. Load A as vec4 when K % 4 == 0. ### Description <!-- Describe your changes. --> Optimize the Intel subgroup GEMM/MatMul kernels in the WebGPU EP with two changes, both gated on the Xe-3LPG architecture: vec4 A loads: when K is a multiple of 4, A is loaded from global memory as vec4 (4 consecutive K elements per load) via cooperative subgroup loading, instead of scalar loads. Double-buffered B tile: for fp16 B inputs, the B tile in workgroup memory is double-buffered, prefetching the next tile while computing on the current one. This overlaps global-memory load latency with compute and reduces from 2 workgroupBarriers per K-loop iteration to 1. Both `a_vec4` and `b_is_fp16` are added to the program CacheHint so distinct pipelines are cached per configuration. On other architectures the kernels fall back to scalar A loads and a single B buffer, preserving previous behavior for shared memory limitation and registers pressure. Measured speedups on Xe-3LPG (avg ~12.7%): Model Speedup jina-clip-v1-version-fp16 13.4% sd-v1.5-text-encoder-demo 15.9% florence-2-base-decoder-fp16 13.3% moondream2-vision-encoder-fp16 11.4% sd-turbo-text-encoder-fp16-demo-layernorm 9.6% ### Motivation and Context <!-- - Why is this change required? What problem does it solve? - If it fixes an open issue, please link to the issue here. --> The Intel subgroup matmul kernels were memory-bound on A loads and incurred two workgroup barriers per K tile. Loading A as vec4 cuts the number of global-memory accesses, and double-buffering the B tile hides load latency behind compute, improving throughput on the fp16 vision/text-encoder workloads above without regressing other architectures.