onnxruntime

a88c1168 - [MLAS] AVX-512 16-wide Erf kernel and NCHWc reorder transpose for MobileClip-S0 model (#31958)

[MLAS] AVX-512 16-wide Erf kernel and NCHWc reorder transpose for MobileClip-S0 model (#31958) **[MLAS] AVX-512 optimizations for MobileClip-S0 FP32 CPU inference** * Added a **16-wide AVX-512 Erf kernel** for standalone ONNX Erf operations, replacing the previous 8-wide implementation on AVX-512 hardware. * Implemented a **single-pass 16×16 AVX-512 NCHWc reorder transpose**, replacing the SSE2-based 4-wide sub-transpose approach for block-16 data reordering. The performance numbers taken in STRIX 365 with different thread configurations: <img width="974" height="116" alt="image" src="https://github.com/user-attachments/assets/a330b407-9d61-45f7-b6a5-9a08a774d6fc" /> NOTE: The performance numbers were tested on July 31st **STRIX 365 configuration:** AMD Ryzen AI 9 365 (Strix Point) w/ Radeon 880M **Target Model:** MobileClip-S0 (FP32, CPU) **Unit tests were added:** **test_erf.cpp** - MlasComputeErf vs std::erf within polynomial accuracy tolerance — sweeps buffer lengths straddling the 16-lane boundary to cover both the AVX-512 main loop and masked-tail path - Direct comparison of MlasErfKernelAvx512F vs the base MlasErfKernelFma3 with ≤1 ULP agreement — covers NaN propagation, ±inf, denormals, saturation - Measured divergence on AVX-512 hardware: 0 ULP (bit-exact); 1 ULP is kept as the cross-microarchitecture contract **test_reorder_input.cpp** - MlasReorderInputNchw (NCHW→NCHWc) vs scalar reference via memcmp - Sweeps channel counts 1–47: exact 16-channel blocks exercise the new MlasReorderInputNchwBlock16Avx512F fast path; partial blocks exercise the scalar tail - Multiple spatial sizes covered --------- Co-authored-by: Manogna-Sree <elisetti.manognasree@multicorewareinc.com>