llvm-project

0d14772a - [RISCV][P-ext] Add isel patterns for for macc*.h00/macc*.w00. (#190444)

[RISCV][P-ext] Add isel patterns for for macc*.h00/macc*.w00. (#190444) The RV32 macc*.h00 instructions take the lower half words from rs1 and rs2, compute the full word product by extending the inputs, and add to rd. The RV64 macc*.w00 is similar but operates on words and produces a double word result. I've restricted this to case where the multiply has a single use. We don't have a general macc that multiplies the full xlen bits of rs1 and rs2, so I'm allowing the input to be sext_inreg/and or have sufficient sign/zero bits according to ComputeNumSignBits/computeKnownBits. We should also add mul*.h00/mul.*w00 patterns, but those we should restrict to at least one input being sext_inreg/and and prefer regular mul when there are no sext_inreg/and.