llvm-project

1cee4fa9 - [RISCV] Update the vector integer division cycle in SiFive7 scheduling model (#159468)

[RISCV] Update the vector integer division cycle in SiFive7 scheduling model (#159468) Vector integer division in SiFive7 processes a single bit at a time up to 4 elements. This patch updates to reflect this behavior. Co-authored-by: Michael Maitland <michaeltmaitland@gmail.com>