llvm-project

1d6607d5 - [AMDGPU] Remove alignment constraint from spill pseudos (#177317)

[AMDGPU] Remove alignment constraint from spill pseudos (#177317) Spill pseudo opcodes don't require target reg class alignment constraint. For targets which do have alignment constraints, lower the spills to 32-bit accesses. Update the machine verifier accordingly. Sgpr spill pseudos didn't enforce alignment constraints. Modify vgpr spills reg class to not enforce them either.