llvm-project

1d9762a0 - [RISCV] Add scheduling models for `sifive-x160` and `sifive-x180` (#187089)

[RISCV] Add scheduling models for `sifive-x160` and `sifive-x180` (#187089) Assign scheduling models to `sifive-x160` and `sifive-x180`. Currently both of them share the same model, which is a variant of the SiFive7 scheduling model with VLEN=128. Because of this commonality, most tests only use `-mcpu=sifive-x180`, whose instruction set is a superset of `sifive-x160`'s.