llvm-project

4c5b1c4e - [RISCV] Add `sifive-x160` and `sifive-x180` processor definitions (#186264)

[RISCV] Add `sifive-x160` and `sifive-x180` processor definitions (#186264) This PR adds new processor definitions for two SiFive cores: - X160 (https://www.sifive.com/document-file/sifive-intelligence-x160-gen2-product-brief): A RV32 core with Zve32f - X180 (https://www.sifive.com/document-file/sifive-intelligence-x180-gen2-product-brief): A RVV-capable RV64 core Both of them have VLEN=128. Scheduling model supports will be added in follow-up patches.