llvm-project
[RISCV] Add `sifive-x160` and `sifive-x180` processor definitions
#186264

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[RISCV] Add `sifive-x160` and `sifive-x180` processor definitions #186264

mshockwave merged 2 commits into llvm:main from mshockwave:patch/riscv/sifive-x160-x180

[RISCV] Add `sifive-x160` and `sifive-x180` processor definitions

f9dad998

mshockwave requested a review from

lenary 60 days ago

mshockwave requested a review from

tclin914 60 days ago

mshockwave requested a review from

topperc 60 days ago

mshockwave requested a review from

wangpc-pp 60 days ago

llvmbot added backend:RISC-V

llvmbot added clang:driver

wangpc-pp commented on 2026-03-13

fixup! Update release note

e15dcb01

lenary approved these changes on 2026-03-13

wangpc-pp approved these changes on 2026-03-14

mshockwave merged 4c5b1c4e into main 57 days ago

mshockwave deleted the patch/riscv/sifive-x160-x180 branch 57 days ago

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wangpc-pp

lenary

tclin914

topperc

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