[RISCV][P-ext] Add initial 64-bit support for RV32. (#197093)
Most operations are set to expand. A few operations that were easy to
support using isel patterns have been added. concat_vectors and
extract_subvector are supported in order to allow type legalization to
split 64-bit vectors into 32-bit vectors around the supported
operations.
Loads and stores are custom split into two i32 scalars or two v4i8/v2i16
vectors.
I've added new opcodes to build and split vectors into 2 GPRs at
function arguments and returns. These are similar to BuildPairF64 and
SplitF64 nodes we use for RV32D soft float. Long term we might want to
use concat_vectors/build_vector and extract_subvector/extract_vectorelt.
llvm-project
5e4a21a1 - [RISCV][P-ext] Add initial 64-bit support for RV32. (#197093)
