llvm-project

6336cc85 - [AtomicExpand][NVPTX] Fix integer vector cmpxchg loops and partword atomicrmw (#211497)

[AtomicExpand][NVPTX] Fix integer vector cmpxchg loops and partword atomicrmw (#211497) After https://github.com/llvm/llvm-project/pull/190716, we now allow integer vector `atomicrmw`, and these should be expanded using `cmpxchg` loops. Currently, these are throwing an assert in `NVPTXISelLowering.cpp`: `assert(Ty->isIntegerTy() && "Ty should be integer at this point");` here I fix that. Second, we are handling partword integer vector `cmpxchg` loops (namely, `<2 x i8>` incorrectly in some cases. The first issue is for `Add` and `Sub`, where we optimize by performing the operation on the word size. This works because even if we overflow or underflow the partword, we handle this by masking back on the the other original loaded bits that we are not operating on. We can't, however, implement a `<2 x i8>` add using a scalar 32-bit add, because the vector variant overflows lane-wise, which can't be emulated with a scalar 32-bit add. I think there might be a way to implement it with a `<4 x i8>` add, but I'm not sure if it's worth it, maybe I'll add that in the future. For now, just go the normal route of extracting out the `<2 x i8>` from the word and performing the `Add` and `Sub` on `<2 x i8>`. Third, for `widenPartwordAtomicRMW`, this operates on `Or`, `Xor`, `And`, all of which the corresponding scalar operation works the same as the integer vector operation. So we can implement these using the scalar word-size operation, we were just missing a `bitcast` from the vector to the scalar.