llvm-project

aa2dac40 - [DAG] SimplifyDemandedBits - fold FSHR(X,Y,Amt) -> SRL(Y,Amt) (#182294)

[DAG] SimplifyDemandedBits - fold FSHR(X,Y,Amt) -> SRL(Y,Amt) (#182294) If a FSHR node's DemandedBits mask and maximum shift amount doesn't demand any bits from the X upper register, then simplify to a SRL node. FSHL is less useful but we could add it as a future patch if there's interest Based off a discussion on #182021