llvm-project
[DAG] SimplifyDemandedBits - fold FSHR(X,Y,Amt) -> SRL(Y,Amt)
#182294

Merged

[DAG] SimplifyDemandedBits - fold FSHR(X,Y,Amt) -> SRL(Y,Amt) #182294

RKSimon merged 7 commits into llvm:main from RKSimon:dag-demanded-fshr

[DAG] SimplifyDemandedBits - fold FSHR(X,Y,Amt) -> SRL(Y,Amt)

54888dd5

Add legality check

991c6264

RKSimon marked this pull request as ready for review 54 days ago

llvmbot added backend:X86

RKSimon requested a review from

jayfoad 54 days ago

llvmbot added llvm:SelectionDAG

RKSimon requested a review from

phoebewang 54 days ago

RKSimon requested a review from

topperc 54 days ago

topperc commented on 2026-02-19

uint64_t -> unsigned

08d16849

topperc commented on 2026-02-19

Require the shift amount is in bounds (otherwise we have to add a URE…

2288e21e

Limit the fold to pow2 types and allow general shift amount bounds

b345fcf3

topperc commented on 2026-02-19

Use APInt::getLimitedValue

afd3c84a

topperc approved these changes on 2026-02-19

Merge branch 'main' into dag-demanded-fshr

3ec9f48c

RKSimon enabled auto-merge (squash) 54 days ago

RKSimon merged aa2dac40 into main 54 days ago

RKSimon deleted the dag-demanded-fshr branch 54 days ago

jayfoad commented on 2026-02-20

Reviewers

topperc

jayfoad

phoebewang

Assignees

No one assigned

Labels

backend:X86 llvm:SelectionDAG

Milestone

No milestone