llvm-project
c4806dbd - [RISCV] Fold LI 1 / SLLI into BSETI during i64 materialization (#142348)

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128 days ago
[RISCV] Fold LI 1 / SLLI into BSETI during i64 materialization (#142348) My first approach was to avoid emitting LI 1 / SLLI in the first place. Unfortunately, that favors BSETI C / ADDI -1 over LI -1 / SRLI 64-C even though the latter has both instructions compressible. This is because the code assumes in several places that a two-instruction sequence (here: BSETI / ADDI) cannot be improved. Another possible approach would be to keep LI 1 / SLLI if it is to be later replaced with SRLI. This would be harder to grasp than eventually patching LI 1 / SLLI with BSETI.
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  • llvm
    • lib/Target/RISCV/MCTargetDesc
      • File
        RISCVMatInt.cpp
    • test/CodeGen/RISCV
      • imm.ll
      • zbb-logic-neg-imm.ll