llvm-project

c5dbaa80 - [lldb][RISCV] Support RVV register access

[lldb][RISCV] Support RVV register access Support RISC-V vector register context (2/3) Add support for reading and writing RISC-V vector (RVV) registers through the native register context on Linux. This enables LLDB to access all 32 vector registers (v0–v31) and the vector CSR registers during debugging sessions.