[X86][ACEV1] Address review comments
- Drop the AMX_TILE dependency; under acev1 enable only the AMX
instructions that ACE v1 actually shares.
- Namespace the ACE-invented intrinsics under llvm.x86.acev1.* and leave
the shared AMX-AVX512 ones in the flat llvm.x86.* namespace.
- Sync the public intrinsic and builtin names with GCC, and add the
helper macros from the ACE v1 spec.
- Tighten Sema checking of the outer-product group bits, and add driver,
preprocessor and feature-error test coverage.
- Spell BSR0 literally in the AsmStrings with Defs/Uses instead of
carrying it as a custom operand, which removes the bespoke handling
from X86AsmParser and both instruction printers.
- Drop the unused BSR register class; like TMMCFG, BSR0 needs only its
X86Reg definition and the getReservedRegs entry.
- Adopt the operand-type record naming convention, 't' for a TILE and
'e' for a GR32 index, on both the instructions and their pseudos,
retiring the ad-hoc _REG suffix.
- Use WriteSystem rather than WriteVecLogic for the tile outer products
and the BSR moves.
- Pass tiles by pointer in the unit tests, and drop comments that only
restate the code.
