llvm-project
[RISCV] Add unit strided load/store to whole register peephole
#100116

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[RISCV] Add unit strided load/store to whole register peephole #100116

lukel97 merged 5 commits into llvm:main from lukel97:vector-peephole-whole-register-load-store

Precommit tests

4748edf0

[RISCV] Add unit strided load/store to whole register peephole

02605fd6

lukel97 requested a review from

preames 1 year ago

lukel97 requested a review from

topperc 1 year ago

lukel97 requested a review from

wangpc-pp 1 year ago

lukel97 requested a review from

yetingk 1 year ago

llvmbot added backend:RISC-V

lukel97 commented on 2024-07-23

wangpc-pp commented on 2024-07-23

Reword comment

da9f0e97

Remove non-existent passthru operand in comment

bcf97fef

wangpc-pp approved these changes on 2024-07-24

Mention we're removing passthrus

d1afc0e7

lukel97 merged b91c75fc into main 1 year ago

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preames

topperc

yetingk

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backend:RISC-V

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