llvm-project
[RISCV] Add TT-Ascalon-d8 processor
#115100
Merged
Go
Login via GitHub
Home
Pricing
FAQ
Install
Login
via GitHub
Overview
Commits
4
Changes
View On
GitHub
[RISCV] Add TT-Ascalon-d8 processor
#115100
mshockwave
merged 4 commits into
llvm:main
from
ppenzin:tt-ascalon-d8
[RISCV] Add TT-Ascalon-d8 processor
246f1374
llvmbot
added
clang
llvmbot
added
backend:RISC-V
llvmbot
added
clang:driver
dtcxzyw
requested a review
from
preames
1 year ago
dtcxzyw
requested a review
from
topperc
1 year ago
dtcxzyw
requested a review
from
wangpc-pp
1 year ago
topperc
commented on 2024-11-06
lukel97
commented on 2024-11-06
wangpc-pp
commented on 2024-11-06
Fix ident and features
6f980c73
lukel97
commented on 2024-11-07
Rewrite extension list using RVA23
34cc9f8c
wangpc-pp
approved these changes on 2024-11-11
One feature check per line
20305c87
lukel97
approved these changes on 2024-11-12
mshockwave
approved these changes on 2024-11-15
topperc
approved these changes on 2024-11-15
mshockwave
merged
41c86ca7
into main
1 year ago
Login to write a write a comment.
Login via GitHub
Reviewers
topperc
mshockwave
lukel97
wangpc-pp
michaelmaitland
preames
Assignees
No one assigned
Labels
clang
backend:RISC-V
clang:driver
Milestone
No milestone
Login to write a write a comment.
Login via GitHub