Adding support in llvm-exegesis for Aarch64 for handling FPR64/128, PPR16 and ZPR128 reg class. #127564
Adding support for FPR64/128, PPR16 and ZPR128 in setReg of llvm-exeg…
624a7eee
Adding support for FPR64/128, PPR16 and ZPR128 in setReg of llvm-exeg…
4c4d605b
Merge branch 'main' into llvm-exegesis-setreg
f8ce0ccb
Added assert that Value is in range for the generated instructions an…
d34cb6d1
Merge branch 'llvm:main' into llvm-exegesis-setreg
566081a0
Merge branch 'llvm:main' into llvm-exegesis-setreg
803b9e97
Merge branch 'llvm-exegesis-setreg' of github.com:lakshayk-nv/llvm-pr…
3589838a
Added combined testfile for register initialization (PPR,ZPR,FPR64/12…
53b9f0b4
Deleted Indvidual testfiles
caebb7b7
Modified: requirement(aarch64) check only required once for a test
230aade9
Modified: PPR register class should be set with immediate value 31 fo…
aab854bc
Modified: Testcases to check disassembly, apart from setReg warning a…
f1e561ce
Modified: Fixed Typo in assertion message
25b02b6b
Modified: Simplified regex checks for disassembly
b83b52de
Modified: Testcases to strictly check correct order of instruction in…
433b62e9
Modified: Stricter asserts for checking immediate (Value) to be set i…
482a0a3e
Modified: Base-instruction of FPR64 reg class to MOVID & ZPR reg clas…
951e05e6
Modified: Updated testcases checks for disassembly as be base instruc…
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Modified: reverted headers
b5853a94
Modified: Simplified testfile to check only disassembly.
2c16af65
Modified: Removed redundant comments and asserts.
c21ee8bf
Modified: Revert back to asserting bit width for GPR Register classes
5cda550a
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