llvm-project
[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM
#129690
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[CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM #129690

vikramRH merged 7 commits into llvm:main from vikramRH:post_ra_machine_sink_npm
vikramRH
vikramRH [CodeGen][NewPM] Port "PostRAMachineSink" pass to NPM
4ccbc386
vikramRH vikramRH requested a review from arsenm arsenm 249 days ago
vikramRH vikramRH requested a review from aeubanks aeubanks 249 days ago
vikramRH vikramRH requested a review from paperchalice paperchalice 249 days ago
vikramRH vikramRH requested a review from cdevadas cdevadas 249 days ago
vikramRH vikramRH requested a review from optimisan optimisan 249 days ago
llvmbot llvmbot added backend:AArch64
llvmbot llvmbot added backend:AMDGPU
llvmbot llvmbot added backend:SystemZ
llvmbot llvmbot added backend:X86
llvmbot llvmbot added debuginfo
llvmbot
llvmbot
arsenm
arsenm approved these changes on 2025-03-04
arsenm arsenm added llvm:codegen
optimisan
optimisan commented on 2025-03-04
vikramRH chain preserveAnalysis calls
5e8b9494
optimisan
optimisan commented on 2025-03-05
vikramRH keep temp variable for preservedAnalyses
efd8b50b
arsenm
arsenm approved these changes on 2025-03-10
optimisan
optimisan approved these changes on 2025-03-10
vikramRH Merge branch 'main' into post_ra_machine_sink_npm
5cec0e36
github-actions
vikramRH cleanup MachinePassRegistry.def
20a9aeac
vikramRH clang-format
53687fd5
optimisan
optimisan approved these changes on 2025-05-02
vikramRH Merge branch 'main' into post_ra_machine_sink_npm
4810aec5
arsenm
arsenm approved these changes on 2025-07-10
vikramRH vikramRH merged fcd4a2fe into main 121 days ago

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backend:AArch64 backend:AMDGPU backend:SystemZ backend:X86 llvm:codegen debuginfo
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