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WIP: RegisterCoalescer: Expand source register class to coalesce subreg inserts
#130879
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WIP: RegisterCoalescer: Expand source register class to coalesce subreg inserts #130879

arsenm wants to merge 23 commits into main from users/arsenm/register-coalescer/inflate-source-reg-class-subreg-insert
arsenm
arsenm arsenm changed the title xxx - Add tests for coalescer bug report WIP: 282 days ago
arsenm arsenm changed the title WIP: WIP: RegisterCoalescer: Expand source register class to coalesce subreg inserts 282 days ago
arsenm
arsenm arsenm added backend:AMDGPU
arsenm arsenm requested a review from jrbyrnes jrbyrnes 282 days ago
llvmbot
github-actions
Base automatically changed from users/arsenm/register-coalescer/amdgpu-baseline-test-inflate-source-reg-class-subreg-insert to main 282 days ago
arsenm xxx - Add tests for coalescer bug report
c44cf2c2
arsenm Add ARM testcase
08d99d00
arsenm RegisterCoalescer: Expand source register class to coalesce subreg in…
9fdf6f9b
arsenm test update
45427e3c
arsenm Hack up the class
93da7deb
arsenm good test update
4a016b35
arsenm hack
b67c8dc8
arsenm Factor into func
8ff1b922
arsenm unbreak
e3b07171
arsenm Debug print
26624fce
arsenm XXX get largest dstrc too
16cc38ee
arsenm debug print
4313086b
arsenm work on class adjustment
4baac124
arsenm More debug
fa2db6b2
arsenm test updates
7ecf43b2
arsenm find class work
a04fdf9c
arsenm comment
4fc92126
arsenm test updates
59cfd65a
arsenm test update restore
df2e0ec7
arsenm one use
e36f30c7
arsenm Use TRI.getMatchingSuperRegClass in loop
803342fa
arsenm junk
3af1561e
arsenm test consistency
34a866b2
arsenm arsenm force pushed from 4aa5ce7d to 34a866b2 282 days ago
jrbyrnes
arsenm

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