llvm-project
[RISCV] Add sext_inreg patterns for XAndesPerf nds.bfos instruction
#139714

Merged

[RISCV] Add sext_inreg patterns for XAndesPerf nds.bfos instruction #139714

tclin914 merged 3 commits into llvm:main from tclin914:andes-extension-codegen-bfo

tclin914 requested a review from

kito-cheng 1 year ago

tclin914 requested a review from

topperc 1 year ago

tclin914 requested a review from

wangpc-pp 1 year ago

llvmbot added backend:RISC-V

topperc commented on 2025-05-13

[RISCV] Add sext_inreg patterns for XAndesPerf nds.bfos instruction

0e81d7c3

Remove the pattern for sign extending in reg from i32 to i64

200668ba

clang format

285c5096

tclin914 force pushed to 200668ba 1 year ago

tclin914 requested a review from

svs-quic 1 year ago

svs-quic approved these changes on 2025-05-16

tclin914 merged c78e6bbd into main 1 year ago

tclin914 deleted the andes-extension-codegen-bfo branch 1 year ago

Reviewers

svs-quic

topperc

kito-cheng

wangpc-pp

Assignees

No one assigned

Labels

backend:RISC-V

Milestone

No milestone