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[RISCV] Update floating point load latency in SiFive7 scheduling model
#159462

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[RISCV] Update floating point load latency in SiFive7 scheduling model #159462

mshockwave merged 1 commit into llvm:main from mshockwave:patch/riscv/sifive7-sched-fp-load

[RISCV] Update floating point load latency in SiFive7 scheduling model

1735134b

mshockwave requested a review from

lenary 52 days ago

mshockwave requested a review from

mikhailramalho 52 days ago

mshockwave requested a review from

topperc 52 days ago

mshockwave requested a review from

wangpc-pp 52 days ago

llvmbot added backend:RISC-V

wangpc-pp approved these changes on 2025-09-18

mshockwave merged a3f901f7 into main 51 days ago

mshockwave deleted the patch/riscv/sifive7-sched-fp-load branch 51 days ago

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wangpc-pp

lenary

mikhailramalho

topperc

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