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[InlineSpiller][AMDGPU] Implement subreg reload during RA spill
#175002
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[InlineSpiller][AMDGPU] Implement subreg reload during RA spill #175002

cdevadas wants to merge 3 commits into users/cdevadas/precommit-subreg-reload-test from users/cdevadas/subreg-reload
cdevadas
cdevadas
cdevadas cdevadas requested a review from arsenm arsenm 276 days ago
cdevadas cdevadas requested a review from easyonaadit easyonaadit 276 days ago
cdevadas cdevadas requested a review from MatzeB MatzeB 276 days ago
cdevadas cdevadas requested a review from qcolombet qcolombet 276 days ago
cdevadas cdevadas requested a review from rampitec rampitec 276 days ago
cdevadas cdevadas requested a review from rovka rovka 276 days ago
cdevadas cdevadas requested a review from shiltian shiltian 276 days ago
cdevadas cdevadas marked this pull request as ready for review 276 days ago
llvmbot llvmbot added backend:ARM
llvmbot llvmbot added backend:AArch64
llvmbot llvmbot added backend:AMDGPU
llvmbot llvmbot added backend:Hexagon
llvmbot llvmbot added backend:MIPS
llvmbot llvmbot added backend:MSP430
llvmbot llvmbot added backend:RISC-V
llvmbot llvmbot added backend:PowerPC
llvmbot llvmbot added backend:Sparc
llvmbot llvmbot added backend:SystemZ
llvmbot llvmbot added backend:X86
llvmbot llvmbot added llvm:codegen
llvmbot llvmbot added llvm:regalloc
llvmbot llvmbot added backend:m68k
llvmbot llvmbot added backend:CSKY
llvmbot llvmbot added backend:NVPTX
llvmbot llvmbot added backend:ARC
llvmbot llvmbot added backend:loongarch
llvmbot llvmbot added backend:Xtensa
llvmbot llvmbot added backend:Lanai
llvmbot
llvmbot
cdevadas
cdevadas commented on 2026-01-08
arsenm
arsenm commented on 2026-01-08
arsenm
arsenm commented on 2026-01-08
cdevadas cdevadas force pushed to 2a12cb5b 276 days ago
rovka
rovka commented on 2026-01-09
cdevadas cdevadas force pushed from 2a12cb5b 272 days ago
cdevadas cdevadas force-pushed the users/cdevadas/precommit-subreg-reload-test branch from c2e3b552 272 days ago
cdevadas cdevadas force-pushed the users/cdevadas/precommit-subreg-reload-test branch to 2b2772b2 272 days ago
cdevadas cdevadas force pushed to b2219060 272 days ago
qcolombet
qcolombet commented on 2026-01-12
cdevadas cdevadas force-pushed the users/cdevadas/precommit-subreg-reload-test branch from 2b2772b2 to 12d1aa0c 271 days ago
cdevadas cdevadas force pushed from b2219060 to 070b3e99 271 days ago
cdevadas
qcolombet
qcolombet commented on 2026-01-23
easyonaadit easyonaadit force pushed from 070b3e99 to 829c8e93 72 days ago
easyonaadit easyonaadit force-pushed the users/cdevadas/precommit-subreg-reload-test branch from 12d1aa0c to 841b2690 72 days ago
easyonaadit easyonaadit force pushed from 829c8e93 to ee9bc033 12 days ago
easyonaadit easyonaadit force-pushed the users/cdevadas/precommit-subreg-reload-test branch from 841b2690 to 4bc23d4e 12 days ago
github-actions
easyonaadit easyonaadit force pushed from ee9bc033 to 7a5fcfb1 12 days ago
github-actions
github-actions
cdevadas [InlineSpiller][AMDGPU] Implement subreg reload during RA spill
9fe06440
easyonaadit Refactor subreg spilling logic.
94a6d826
easyonaadit easyonaadit force-pushed the users/cdevadas/precommit-subreg-reload-test branch from 4bc23d4e to a23820b2 11 days ago
easyonaadit easyonaadit force pushed from 8653a63a to 94a6d826 11 days ago
easyonaadit generate stack offsets from the subreg instead of using lanebitmasks.
2d6f7471

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backend:ARM backend:AArch64 backend:AMDGPU backend:Hexagon backend:MIPS backend:MSP430 backend:RISC-V backend:PowerPC backend:Sparc backend:SystemZ backend:X86 llvm:codegen llvm:regalloc backend:m68k backend:CSKY backend:NVPTX backend:ARC backend:loongarch backend:Xtensa backend:Lanai
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