llvm-project
[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload
#175581
Merged

[CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot for subreg-reload #175581

cdevadas
cdevadas [CodeGen][InlineSpiller] Add SubReg argument to loadRegFromStackSlot …
eee8d54d
cdevadas
cdevadas cdevadas requested a review from arsenm arsenm 20 days ago
cdevadas cdevadas requested a review from easyonaadit easyonaadit 20 days ago
cdevadas cdevadas requested a review from MatzeB MatzeB 20 days ago
cdevadas cdevadas requested a review from qcolombet qcolombet 20 days ago
cdevadas cdevadas requested a review from rovka rovka 20 days ago
cdevadas cdevadas marked this pull request as ready for review 20 days ago
llvmbot llvmbot added backend:ARM
llvmbot llvmbot added backend:AArch64
llvmbot llvmbot added backend:AMDGPU
llvmbot llvmbot added backend:Hexagon
llvmbot llvmbot added backend:MIPS
llvmbot llvmbot added backend:MSP430
llvmbot llvmbot added backend:RISC-V
llvmbot llvmbot added backend:PowerPC
llvmbot llvmbot added backend:Sparc
llvmbot llvmbot added backend:SystemZ
llvmbot llvmbot added backend:X86
llvmbot llvmbot added backend:m68k
llvmbot llvmbot added backend:CSKY
llvmbot llvmbot added backend:NVPTX
llvmbot llvmbot added backend:ARC
llvmbot llvmbot added backend:loongarch
llvmbot llvmbot added backend:Xtensa
llvmbot llvmbot added backend:Lanai
llvmbot
llvmbot
arsenm arsenm added llvm:regalloc
arsenm
arsenm approved these changes on 2026-01-12
cdevadas used RISCV::NoSubRegister instead of 0.
e69657c6
lenary
qcolombet
qcolombet approved these changes on 2026-01-12
cdevadas
cdevadas cdevadas merged 9e160602 into main 19 days ago
cdevadas cdevadas deleted the users/cdevadas/add-subreg-arg-to-loadRegFromStackSlot branch 19 days ago
llvm-ci
llvm-ci

Login to write a write a comment.

Login via GitHub

Assignees
No one assigned
Labels
Milestone