PR #99932 [GISEL][RISCV] RegBank Scalable Vector Load/Store

[GISEL][RISCV] RegBank Scalable Vector Load/Store #99932

jiahanxie353 merged 8 commits into llvm:main from jiahanxie353:ld-st-regbank

jiahanxie353 closed this 1 year ago

jiahanxie353 reopened this 1 year ago

jiahanxie353 force pushed from 460c670e to 28c2cc5b 1 year ago

jiahanxie353 commented on 2024-07-22

jiahanxie353 requested a review from

michaelmaitland 1 year ago

topperc commented on 2024-07-22

jiahanxie353 force pushed from 28c2cc5b to 9934fadd 1 year ago

jiahanxie353 commented on 2024-07-30

topperc commented on 2024-07-30

michaelmaitland commented on 2024-07-30

michaelmaitland approved these changes on 2024-07-30

michaelmaitland marked this pull request as ready for review 1 year ago

llvmbot added backend:RISC-V

llvmbot added llvm:regalloc

llvmbot added llvm:globalisel

jiahanxie353 force pushed to ce127646 1 year ago

topperc requested changes on 2024-07-31

jiahanxie353 force pushed from ce127646 to 80a710e8 1 year ago

topperc approved these changes on 2024-07-31

jiahanxie353 force pushed from 80a710e8 to ce3892a6 1 year ago

75d36b90

made some changes based on review

a700261b

use type size instead of unsigned when getting value mapping

382cbd71

OpsMapping[1] is always GPR; use getFixedValue when type is not vector

6f2b1ae5

use getFixedValue() from size directly

7683e28b

correct testing code

c04c4ec4

early break if Ty isVector

93fcb523

update test files (previously using the result of regbankselect direc…

2fe4c155

jiahanxie353 force pushed from ce3892a6 to 2fe4c155 1 year ago

jiahanxie353 merged 1c66ef91 into main 1 year ago

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topperc

michaelmaitland

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backend:RISC-V llvm:regalloc llvm:globalisel

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llvm-project [GISEL][RISCV] RegBank Scalable Vector Load/Store #99932 Merged

[GISEL][RISCV] RegBank Scalable Vector Load/Store #99932

llvm-project
[GISEL][RISCV] RegBank Scalable Vector Load/Store
#99932

Merged