PR #32540 [MLAS] Riscv64 rvv kernel optimizations

[MLAS] Riscv64 rvv kernel optimizations #32540

mirounga merged 5 commits into microsoft:main from Zestion:riscv64-rvv-kernel-optimizations

Reduce once per row in the riscv64 softmax kernels

0ff52591

Carry an accumulator per output position in the riscv64 NCHWc kernels

0ef7fc0e

Choose the riscv64 NCHWc register group from the vector length

6925f2c3

Extend the riscv64 depthwise convolution to any kernel shape

2c04be81

Zestion requested a review from

copilot-pull-request-reviewer 60 days ago

Zestion changed the title ~~Riscv64 rvv kernel optimizations~~ [MLAS] Riscv64 rvv kernel optimizations 60 days ago

copilot-pull-request-reviewer commented on 2026-09-10

Add an RVV activation routine on riscv64

b44bb448

Zestion force pushed from 7a9b090e to b44bb448 60 days ago

mirounga requested a review from

mirounga 54 days ago

mirounga approved these changes on 2026-09-17

mirounga merged a76f0666 into main 53 days ago

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